Since its advent nearly five decades ago, scan has become one of the most influential and industry-proven structured design for test (DFT) technology. It allows a direct access to memory elements of a circuit under test (CUT) by reusing them to form shift registers in a test mode. The operative paradigm is then to employ automatic test equipment (ATE) or another source of test patterns to feed serial inputs of the scan chains, with the same ATE or a test response compactor capturing test responses that leave the scan chains through their serial outputs. As all scan cells are typically controlled by a single scan enable signal, scan chains remain functionally indistinguishable, i.e., they all either shift data in and out or capture test responses. The resultant high controllability and observability of internal nodes made it possible to automatically generate high quality tests and to debug the first silicon. Moreover, simple architecture of scan chains enables their automated stitching and insertion supported by electronic design automation (EDA) tools.
With the scan-based test paradigm firmly in place, several more advanced DFT technologies have been proposed. Noticeably, many logic built-in self-test (LBIST) schemes employ scan as their operational baseline to achieve high quality test while using a limited volume of test data. Usually, these solutions comprise a pseudorandom test pattern generator (PRPG) feeding scan chains and a multiple-input signature register (MISR) compacting shifted-out responses. The same rules apply to test data compression where PRPG is typically re-placed with an on-chip test data decompressor.
Drawbacks of scan-based testing are mainly related to the fact that all scan chains are filled with a test pattern before it is applied. As a result, the vast majority of test time is spent on just shifting test data. Consider a design with 100-cell long scan chains. Applying 10,000 double-capture test patterns will require 1,000,000 shift cycles and 20,000 capture cycles. Thus, as low as 2% of cycles are actually spent on testing. In terms of test time, this result would be visibly worse, as the scan shift frequency is usually much lower than that of a capture (functional) mode. In logic BIST, the test time efficiency could be even lower. With 100,000 single-capture test patterns, 10,000,000 cycles are needed for scan shifting, while only 100,000 cycles are deployed to capture test responses. Hence, 99.99% of test time is spent on scan shifting.
Electronics content in vehicles is constantly growing, which enables advanced safety features, new information and entertainment services, and greater energy efficiency. Integrated circuits for the automotive electronics market must adhere to stringent requirements for quality and reliability, which are largely driven by safety standards such as ISO 26262 and Automotive Safety Integrity Level (ASIL) targets. ISO 26262 compliance requires the adoption of more advanced test solutions. In particular, for an integrated circuit to achieve necessary levels of reliability, LBIST capabilities should respond to challenges posed by automotive parts and to support a number of in-field test requirements including an ability to run periodic tests during functional operations. These periodic tests should be performed in short time periods due to strict limits on the length of power-up or idle times. It is thus advantageous to develop test techniques that can shorten test application time without adversely impacting fault coverage.